Having troubles reading this email? Click here http://www.dvcon.org/january.htm DVCon Bulletin January 2004 Welcome to the first issue of the 2004 DVCon Bulletin. This brief monthly email is intended to give you updates and insight into DVCon, the most important and influential conference for design and verification using hardware description languages. We are less than two months away to this years' show. Sponsored by Accellera, the conference will be held in San Jose, California, March 1-3, 2004. Highlights in this issue: Ray Bingham to provide Keynote Address Ray Bingham, President and CEO of Cadence Design Systems, Inc., will deliver the Keynote Address on Tuesday, March 2nd at 8:30am. For more information, please visit http://www.dvcon.com/keynote.html. John Cooley to moderate "Talking Heads" panel Come and hear the well-known talking heads of EDA discuss the issues of the day. On Tuesday, March 2, from 4pm - 5pm, industry opinion makers will address questions such as, "What's your take on US jobs being outsourced to China, India, and Russia? Is System Verilog for real or just Synopsys marketing hype? What ever happened to SystemC? How are those package deals and "free" software affecting the industry? What about Milkyway vs. OpenAccess? Is there an RTL synthesis war starting up? How is the backend war going?" For a list of panelists, please visit http://www.dvcon.com/panel1.html. Special Tutorial Promotion DVCon is looking at ways to greatly reduce the cost for engineers to enroll in the tutorials. In this time of intense budgetary restrictions, DVCon is offering a sponsored tutorial included in the full conference registration fee. The minimal cost for Exhibit-only registrants is $50.00 per sponsored tutorial. Seating is Limited so register now! http://www.dvcon.com/tutpromo.html DVCon Trivia What does the IEEE 1364.1 and 1076.6 standards have in common? Answer is at the bottom of the Bulletin. From the General Chair To get an SOC to actually function in silicon requires a new level of verification to reduce the fear of dead chip and relieve the frustration of a disconnect between actual functionality vs. specified functionality. In short - "verify or die" is the clarion call that drives engineers to demand design languages that are capable of built-in assertion type verification as well as embrace embedded software as an integral part of the system solution on silicon. This call leads to the emergence of an "executable specification" that has integrity of function because verification tools can demonstrate expected, and also unexpected results. This is precisely why at DAC 2003, the emergence of the importance of verification as a discipline was the buzz. For full text of this letter from Frank Weiler, DVCon 2004 General Chair, please visit http://www.dvcon.org/geninfo.html The Latest News on Verification For the latest news on verification from exhibiting companies and standards organizations, please visit http://www.dvcon.com/press.html DVCon Facts This year is the 13th anniversary of the Design and Verification Conference and Exhibition (DVCon). Formerly HDLCon, the conference has been expanded to include valuable information for design engineers, verification engineers, EDA professionals, university researchers and industry leaders. This year there will be 32 regular papers, 4 panels, 6 tutorials and 15 exhibitors. For more information on each session, please visit http://www.dvcon.org/techprog.html Calling all Attendees - Early registration ends February 17, 2004 For more information about registration, please visit http://www.dvcon.com/reg.html. Count Down Only 39 more days until DVCon! To find out about exhibiting and to get more information about the conference, please visit http://www.dvcon.com/exhibits.html. Trivia answer: They both define the synthesizable subsets of the respective HDLs. -------------------------------------------------------------------------------- March 1-3, 2004 Doubletree Hotel San Jose, CA www.dvcon.org -------------------------------------------------------------------------------- You are receiving this email because you have attended or requested information from the Design Verification Conference, or you opt-in from accellera.org. If you would like to take yourself of this list please reply with Remove in the subject line and you will be removed from further DVCon or Accellera correspondence. Thank you!